Current radar signal processors (RSPs) lack eitherperformance or flexibility. Custom soft-core processors exhibitpotential in high-performance signal processing applications,yet remain relatively unexplored in research literature. In thispaper, we use an iterative design methodology to propose a novelsoft-core streaming processor architecture. The datapaths of thisarchitecture are arranged in a circular pattern, with multipleoperands simultaneously flowing between switching multiplexersand functional units each cycle. By explicitly specifyinginstruction-level parallelism and software pipelining, applicationscan fully exploit the available computational resources. Theproposed architecture exceeds the clock cycle performance ofa commercial high-end digital signal processor (DSP) processorby an average factor of 14 over a range of typical operatingparameters in an RSP application.
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